The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the present named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Integrated circuits are often designed as system on chip (SOC) circuits that include various interfaces, firmware, processors, and/or embedded memories. The embedded memories are used for data storage or processing and are generally tested following fabrication of the SOC to identify potential defects. One testing scheme uses a built-in self test (BIST) scheme that sends predetermined test vectors to the memory. A BIST scheme enables testing of the memory “at speed,” i.e., at an operating speed of the target memory.
When the BIST is testing the memory, the remainder of the SOC circuit is not typically running at full functionality or accessing the memory. Accordingly, the current drawn when the memory is undergoing BIST is often relatively small compared to the current drawn if the entire SOC circuit is active. Furthermore, depending on the physical location of the memory on the SOC and the physical layout of the power grid, the I-R voltage drop of the power supply voltage relative to the power supply source could negatively affect the operation of the memory by providing a reduced voltage to the memory when the SOC is at full operation. The I-R voltage drop may be due to the serial resistance of the metal lines providing the power supply. In particular, a memory in a SOC circuit could pass a BIST when the memory is tested without the remainder of the SOC being active, but the memory may have functional failures when the other circuits in the SOC circuit are operating at full functionality and/or accessing the memory.